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    Improving the Dynamic Performance of Bridgeless PFC Controllers with Zero Crossing Detector and Root-Mean-Square Calculation Blocks

    Autor: 
    Pigazo, Alberto
    ;
    Azcondo, Francisco J.
    ;
    Brañas, C.
    ;
    Lamo-Anuarbe, Paula
    ;
    Casanueva, Rosario
    ;
    Díaz, Francisco J.
    Fecha: 
    2023
    Palabra clave: 
    power electronics; PFC Controllers; frequency-locked loop (FLL); Scopus
    Revista / editorial: 
    IEEE
    Citación: 
    A. Pigazo, F. J. Azcondo, C. Brañas, P. Lamo, R. Casanueva and F. J. Díaz, "Improving the Dynamic Performance of Bridgeless PFC Controllers with Zero Crossing Detector and Root-Mean-Square Calculation Blocks," 2023 IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL), Ann Arbor, MI, USA, 2023, pp. 1-6, doi: 10.1109/COMPEL52896.2023.10220445.
    Tipo de Ítem: 
    conferenceObject
    URI: 
    https://reunir.unir.net/handle/123456789/16817
    DOI: 
    https://doi.org/10.1109/COMPEL52896.2023.10220445
    Dirección web: 
    https://ieeexplore.ieee.org/document/10220445/authors#authors
    Resumen:
    Bridgeless Power Factor Correctors (PFC) with a controller utilizing rectified ac variables can benefit from well-established strategies and circuits employed in PFCs with diode-bridge front-end. The grid voltage polarity is detected to compute the rms value of the grid voltage, and also used to generate and route the gate signals for the power devices. However, depending on the implementation, grid voltage disturbances may propagate through the polarity detection and RMS calculation stages, leading to a degradation of the input current and output voltage. This issue is addressed in this manuscript by investigating a single-phase bridgeless totem-pole (TP) PFC through simulation and proposing the replacement of the conventional implementation with a frequency-locked loop (FLL) to enhance the converter dynamics.
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