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dc.contributor.authorPigazo, Alberto
dc.contributor.authorAzcondo, Francisco J.
dc.contributor.authorBrañas, C.
dc.contributor.authorLamo-Anuarbe, Paula
dc.contributor.authorCasanueva, Rosario
dc.contributor.authorDíaz, Francisco J.
dc.date2023
dc.date.accessioned2024-06-27T13:54:50Z
dc.date.available2024-06-27T13:54:50Z
dc.identifier.citationA. Pigazo, F. J. Azcondo, C. Brañas, P. Lamo, R. Casanueva and F. J. Díaz, "Improving the Dynamic Performance of Bridgeless PFC Controllers with Zero Crossing Detector and Root-Mean-Square Calculation Blocks," 2023 IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL), Ann Arbor, MI, USA, 2023, pp. 1-6, doi: 10.1109/COMPEL52896.2023.10220445.es_ES
dc.identifier.isbn9798350316186
dc.identifier.isbn9798350316193
dc.identifier.urihttps://reunir.unir.net/handle/123456789/16817
dc.description.abstractBridgeless Power Factor Correctors (PFC) with a controller utilizing rectified ac variables can benefit from well-established strategies and circuits employed in PFCs with diode-bridge front-end. The grid voltage polarity is detected to compute the rms value of the grid voltage, and also used to generate and route the gate signals for the power devices. However, depending on the implementation, grid voltage disturbances may propagate through the polarity detection and RMS calculation stages, leading to a degradation of the input current and output voltage. This issue is addressed in this manuscript by investigating a single-phase bridgeless totem-pole (TP) PFC through simulation and proposing the replacement of the conventional implementation with a frequency-locked loop (FLL) to enhance the converter dynamics.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.relation.urihttps://ieeexplore.ieee.org/document/10220445/authors#authorses_ES
dc.rightsrestrictedAccesses_ES
dc.subjectpower electronicses_ES
dc.subjectPFC Controllerses_ES
dc.subjectfrequency-locked loop (FLL)es_ES
dc.subjectScopuses_ES
dc.titleImproving the Dynamic Performance of Bridgeless PFC Controllers with Zero Crossing Detector and Root-Mean-Square Calculation Blockses_ES
dc.typeconferenceObjectes_ES
reunir.tag~ARIes_ES
dc.identifier.doihttps://doi.org/10.1109/COMPEL52896.2023.10220445


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