Improved Noise Immunity for Two-Sample PLL Applicable to Single-Phase PFCs

dc.contributor.author	Lamo-Anuarbe, Paula
dc.contributor.author	Azcondo, Francisco J.
dc.contributor.author	Pigazo, Alberto
dc.date	2021
dc.date.accessioned	2022-12-01T14:49:21Z
dc.date.available	2022-12-01T14:49:21Z
dc.identifier.isbn	9781665436359
dc.identifier.uri	https://reunir.unir.net/handle/123456789/13843
dc.description.abstract	Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling frequency used. Low signal-to-noise ratios (SNR) reduce the performance of the Two-Sample (2S) Phase Locked Loop (PLL). This effect can be compensated by including a smoothing filter action without increasing the overall complexity significantly. The resulting 2S with smoothing (2SS) is evaluated and validated by simulation and experimentally over a Totem Pole PFC.	es_ES
dc.language.iso	eng	es_ES
dc.publisher	2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics, COMPEL 2021	es_ES
dc.relation.uri	https://ieeexplore.ieee.org/document/9645988	es_ES
dc.rights	openAccess	es_ES
dc.subject	noise immunity	es_ES
dc.subject	PLL	es_ES
dc.subject	synchronization	es_ES
dc.subject	Scopus(2)	es_ES
dc.subject	WOS(2)	es_ES
dc.title	Improved Noise Immunity for Two-Sample PLL Applicable to Single-Phase PFCs	es_ES
dc.type	conferenceObject	es_ES
reunir.tag	~ARI	es_ES
dc.identifier.doi	https://doi.org/10.1109/COMPEL52922.2021.9645988

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