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Implementation Oriented Two-Sample Phase Locked Loop for Single-Phase PFCs

dc.contributor.authorLamo-Anuarbe, Paula
dc.contributor.authorRuiz, Gustavo A.
dc.contributor.authorAzcondo, Francisco J.
dc.contributor.authorPigazo-López, Alberto
dc.date2020
dc.date.accessioned2021-05-28T07:31:25Z
dc.date.available2021-05-28T07:31:25Z
dc.identifier.isbn9781728171609
dc.identifier.urihttps://reunir.unir.net/handle/123456789/11427
dc.description.abstractA low-resource-consuming digital implementation of the Two-Sample (2S) Phase Locked Loop (PLL)for application in low cost single-phase Power Factor Correction (PFC) converters is proposed. The design reduces the sampling rate of the grid voltage and replaces trigonometric functions by a digital oscillator and divisions by approximations, without reducing the 2S-PLL synchronization capability. The proposal is evaluated and validated with simulations and experimentally.es_ES
dc.language.isoenges_ES
dc.publisher2020 IEEE 21st Workshop on Control and Modeling for Power Electronicses_ES
dc.relation.ispartofseries;nº 9265750
dc.relation.urihttps://ieeexplore.ieee.org/document/9265750es_ES
dc.rightsrestrictedAccesses_ES
dc.subjectcomputational burdenes_ES
dc.subjectdigital implementationes_ES
dc.subjectlow switching frequencyes_ES
dc.subjectphase locked loopes_ES
dc.subjectPLLes_ES
dc.subjectsynchronizationes_ES
dc.subjectScopus(2)es_ES
dc.subjectWOS(2)es_ES
dc.titleImplementation Oriented Two-Sample Phase Locked Loop for Single-Phase PFCses_ES
dc.typeconferenceObjectes_ES
reunir.tag~ARIes_ES
dc.identifier.doihttps://doi.org/10.1109/COMPEL49091.2020.9265750


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