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Implementation Oriented Two-Sample Phase Locked Loop for Single-Phase PFCs
(2020 IEEE 21st Workshop on Control and Modeling for Power Electronics, 2020)
A low-resource-consuming digital implementation of the Two-Sample (2S) Phase Locked Loop (PLL)for application in low cost single-phase Power Factor Correction (PFC) converters is proposed. The design reduces the sampling ...
Improved Noise Immunity for Two-Sample PLL Applicable to Single-Phase PFCs
(2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics, COMPEL 2021, 2021)
Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling ...