Bridgeless Power Factor Correctors (PFC) with a controller utilizing rectified ac variables can benefit from well-established strategies and circuits employed in PFCs with diode-bridge front-end. The grid voltage polarity is detected to compute the rms value of the grid voltage, and also used to generate and route the gate signals for the power devices. However, depending on the implementation, grid voltage disturbances may propagate through the polarity detection and RMS calculation stages, leading to a degradation of the input current and output voltage. This issue is addressed in this manuscript by investigating a single-phase bridgeless totem-pole (TP) PFC through simulation and proposing the replacement of the conventional implementation with a frequency-locked loop (FLL) to enhance the converter dynamics.